Mar. 13, 2023
This article provides guidance on printed circuit board (PCB) layout and wiring to help designers avoid such noise problems. The example switching regulator layout uses a dual channel synchronous switching controller ADP1850. The first step is to determine the current path of the regulator. The current path then determines the location of the device in this low noise layout routing design.
PCB layout and wiring guide
Step 1: Determine the current path
In a switching converter design, high current paths and low current paths are very close to each other. AC (AC) paths carry spikes and noise, high DC (DC) paths produce considerable voltage drops, and low current paths tend to be sensitive to noise. The key to proper PCB layout is to determine the critical path, then arrange the components, and provide enough copper area so that high current does not destroy low current. Poor performance is ground bounce and noise injection into the IC and the rest of the system.
Figure 1 shows a synchronous step-down regulator design that includes a switching controller and the following external power components: high end switch, low end switch, inductor, input capacitor, output capacitor, and bypass capacitor. The arrows in Figure 1 indicate the high switching current direction. These power components must be carefully placed to avoid undesirable parasitic capacitors and inductors that can lead to excessive noise, overshoot, ringing oscillation, and ground rebound.
Figure 1. Typical switching regulator (showing AC and DC current paths)
Switch current paths such as DH, DL, BST, and SW should be properly arranged after leaving the controller to avoid excessive parasitic inductance. The high delta I/ delta t AC switching pulse current carried by these lines may reach more than 3 A and last several nanoseconds. The high current loop must be small to minimize output ringer oscillations and avoid picking up additional noise.
Low-value, low-amplitude signal paths, such as compensation and feedback devices, are sensitive to noise. These paths should be kept far away from shutdown points and power supply devices to avoid injecting interference noise.
Step 2: Lay out the physical plan
PCB physical planning (floor plan) is very important. The current loop area must be minimized, and the power supply devices must be rationally arranged to make the current flow smoothly and avoid sharp corners and narrow paths. This will help reduce the parasitic capacitance and inductance, thus eliminating grounding bounce.
FIG. 2 shows the PCB layout of a dual output step-down converter with a switching controller ADP1850. Note that the layout of the power supply devices minimizes the current loop area and parasitic inductance. Dashed lines indicate high current paths. Both synchronous and asynchronous controllers can use this physical planning technique. Schottky diodes replace low - end switches in asynchronous controller designs.
Step 3: Power supply devices -- MosFETs and capacitors (input, bypass, and output)
The current waveform at the top and bottom power switches is a pulse with very high delta I/ delta t. Therefore, the path connecting the switches should be as short as possible to minimize noise picked up by the controller and noise transmitted by the inductive loop. When using a pair of DPAK or SO-8 packaged FeTs on one side of the PCB, it is best to rotate the two FeTs in opposite directions SO that the switching node is on the side of the pair of FETs and the high end leakage current is bypassed to the low end source with a suitable ceramic bypass capacitor. It is important to place the bypass capacitor as close to the MOSFEts as possible (see Figure 2) to minimize inductance around the loop that passes through the FETs and the capacitor.
Heat dissipation is considered and connected to strata
Under heavy-duty conditions, the equivalent series resistance (ESR) of the power mosFETs, inductors, and large capacitors produce a significant amount of heat. For effective heat dissipation, the example in Figure 2 places a large area of copper beneath these power components.
The heat dissipation effect of multilayer PCB is better than that of 2-layer PCB. To improve heat dissipation and electrical conductivity, a 2-ounce thickness of copper should be used on top of a standard 1-ounce copper layer. It also helps to have multiple PGND layers connected together through holes. Figure 3 shows that PGND layer is distributed on the top, third and fourth layers of a 4-layer PCB design.
This multilayer approach can isolate noise sensitive signals. As shown in figure 2, the compensation device, soft start capacitor, offset input bypass capacitor and the negative terminal of the output feedback resistance voltage divider are all connected to AGND layer. Please do not directly to any current or delta I/delta t path connected to the isolated AGND layer. AGND formation is a quiet, there is no large current flows through.
Figure 4. AGND to PGND layer connection
AGND layer to extend all the way to the output capacitance, AGND and PGND layer in the negative terminals of the output capacitor is connected to the hole.
Figure 2 shows another connection AGND and PGND layer technology, AGND layer through large capacitance output negative side near the hole connected to PGND layer. Figure 3 shows the cross section of a certain position on the PCB, AGND and PGND layer through large capacitance negative output end near the hole is connected.
Current detection path
In order to avoid the accuracy drop caused by interference noise, the current detection path layout of the current mode switch regulator must be appropriate. Dual-channel applications in particular need to be more focused on eliminating any cross-talk between channels.
The dual-channel step-down controller ADP1850 uses the on-resistance RDS(ON) of the low-end mosfeTs as part of the control loop architecture. This architecture detects the current flowing through the low end mosFETs between the SWx and PGNDx pins. Ground current noise in one channel may be coupled to adjacent channels. Therefore, it is important to make SWx and PGNDx routes as short as possible and place them close to the MOSFETs for accurate current detection. Connections to SWx and PGNDx nodes must be made using Kelvin detection techniques, as shown in Figures 2 and 5. Note that the corresponding PGNDx wiring connects to the source of the low-end MOSFETs. Do not arbitrarily connect the PGND layer to the PGNDx pins.
Figure 5. Grounding technology of the two channels
Feedback and current limiting detection paths
Feedback (FB) and current limiting (ILIM) pins are low signal level inputs, and as such, they are sensitive to capacitive and inductive noise interference. FB and ILIM should avoid routing near high δI/δt. Be careful not to let the cable form a loop, resulting in the increase of bad inductance.
In a switched regulator circuit, the switch (SW) node is the noisiest place because it carries a lot of AC and DC voltage/current. This SW node requires a large area of copper to minimize the resistive pressure drop. Placing the MOSFETs and inductors close to each other on a copper layer minimizes series resistance and inductance.
Figure 6. Buffer and grid resistors Resistance
Grid driven wiring (DH and DL) also deals with high delta I/ delta t, which tends to produce ringing oscillations and overshoot. These routes should be as short as possible. Direct wiring is preferred, avoiding the use of feed through holes. If pass holes must be used, use two pass holes per route to reduce peak current density and parasitic inductance.